1. Field of the Invention
The present invention relates to the field of semiconductor processing. More specifically, the present invention relates to the isolation of active areas on a semiconductor wafer.
2. Related Art
Isolating adjacent active areas is a very essential requirement as device dimensions are scaled down on an integrated circuit (IC). As the scaling gets down below 0.25 um technology, the Local Oxidation of Silicon (LOCOS) isolation scheme fails because the thickness of the grown isolating oxide is not adequate for the narrow space. In addition, the large encroachment associated with the LOCOS scheme makes it difficult to get the required active area width. LOCOS also has high temperature and long oxidation periods. Shallow Trench Isolation (STI) is widely used to isolate active areas in VLSI technologies with critical dimensions less than 0.25 um. This method provides robust isolation when the space between P+ and N+active areas gets down below about 0.80 um since the thickness of the isolation regions is not significantly limited and the encroachment is very small.
The STI process used currently involves creation of trenches of depth of about 3000 angstroms to 4000 angstroms in silicon in regions where isolation spaces are to be formed. The pattern of the spaces is etched in a silicon nitride layer deposited on top of a pad oxide. After the formation of the trench pattern, silicon dioxide is deposited by a Chemical Vapor Deposition (CVD) process to fill the trenches. The oxide is polished using the silicon nitride as the stopping layer. The nitride is then stripped off to get the pattern of the active areas with isolating oxide spaces.
Shallow Trench Isolation however, has its own problems nominally because the oxide in the isolating regions is not grown but deposited and the stress levels in this oxide can become very high. The stress levels may be increased further by the shape of the active/isolation pattern. Active areas with sharp bends or corners are more prone to problems with stress. This stress, combined with the damage caused by plasma etch such as spacer etch lead to the formation of nucleation sites for dislocations. Bombardment by heavy ions such as arsenic during ion implantation can lead to dislocations in the silicon crystal in these sites. These dislocations at the surface when intersecting the source/drain to substrate P-N junctions can give rise to severe reverse leakage in these junctions that can either seriously affect the functionality of a Static Random Access Memory (SRAM) cell or can give rise to very high standby current in the cell.
Stress induced defects are seen near poly lines. When a poly line crosses an active area, there is likely to be a gouge into the active area next to the poly edge due to the poly/spacer etch. The gouge may also generate some nucleation sites for dislocations. The extent of gouge and or dislocation generation is decided by the quality of the oxide at the edge of the active area, which is mainly the liner oxide. Depending on where the poly line intersects the active area, the extent of damage caused by the spacer etch may be different. When the active area is straight, the liner oxide grown after trench etch is stress free and hence may be able to withstand the poly/spacer etch better. On the other hand, when the active area has a corner, the liner oxide grown in this region has high stress and hence may be more prone to gouge when a poly line crosses the corner. Thus in a SRAM cell, a poly line crossing the corner of an active area may give rise to dislocations. This will lead to leakage in the N+ to P-substrate junctions which will lead to failure of the cell.
Accordingly, what is needed is a method and process for the fabrication of an isolation region in a semiconductor which will reduce or eliminate leakage between active areas. What is needed yet is a method and process in which the fabrication time for an isolation region in a semiconductor is reduced. What is also needed is a method and process which allows the further shrinkage of integrated circuits to smaller sizes compatible with the next technology generation. The present invention provides these advantages and others not specifically mentioned above but described in the sections to follow.
A method and process are disclosed for the fabrication of an isolation region in a semiconductor crystal. The method and process may be used in the fabrication of isolation regions used for the separation of adjacent active areas in an integrated circuit. A shallow trench is created on the surface of the semiconductor in regions where isolation spaces are to be formed. A layer of silicon dioxide (LINOX) is then grown over the surfaces of the trench. The LINOX covers roughened regions formed along the surfaces of the trench during its formation.
In one embodiment of the present invention, the liner oxidation recipe calls for growing the LINOX in the presence of oxygen and chlorine at a temperature of about 1000 degrees Centigrade. In one embodiment of the present invention, immediately following the growth of the LINOX, the temperature is increased to about 1050 degrees Centigrade for a period of time sufficient in order to anneal the LINOX. The remaining volume of the trench is then filled with silicon dioxide by Chemical Vapor Deposition (CVD). The surface of the semiconductor is then polished to reveal the pattern of active areas with isolating oxide regions.
In one embodiment of the present invention, the step of annealing the LINOX provides a number of distinct advantages. First of all, annealing greatly reduces stresses in the LINOX and in the surrounding semiconductor material. Annealing also increases the density of the LINOX. Thus annealing increases the LINOX resistance to damage or gouge during any subsequent etching; for instance during a poly/spacer etch. This leads to a reduction in dislocations in the semiconductor crystal and an attendant reduction in electrical leakage around the isolation region. In one embodiment of the present invention, the electrical leakage in a SRAM cell with shallow trench isolated active areas having sharp corners is reduced. A more robust LINOX and a reduction in electrical leakage around an isolation region allows for the further shrinkage of integrated circuit dimensions. In one embodiment of the present invention, a reduction in the dimensions of a Static Random Access Memory (SRAM) cell is made possible. Furthermore, denuding and gettering of the semiconductor are both accomplished during the annealing step which results in a shortening of total processing time. Finally, since gouging of the LINOX no longer occurs where poly/spacer etch overlaps an active area corner, restrictions on the placement of poly lines have been eliminated.